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Following are the results from a series of RAMS and MM5 efficiency tests done at ATMET. These tests were done on a PC Beowulf cluster of 7 1.4 ghz athlon dual-processor machines. Some tests are for different options and some are for different numbers of processors. All are for 1 hr of simulation time, 108 sec coarse tstep, dis-regarding first and last timesteps. All tests were done with MM5 version 3-5 and RAMS version 4.3.
Figure 1: Plot is seconds/timestep (coarse grid timestep) vs. number of processors. Results are plotted for 2, 3, and 4 grid simulations. Also plotted are results from an MM5 8-processor, 3-grid simulation, varying some of the model options and parameterizations. |
Figure 2: Plot is seconds/timestep (coarse grid timestep) vs. number of processors. Results are plotted for 2, 3, and 4 grid simulations. Also plotted are results from an MM5 8-processor, 3-grid simulation, varying some of the model options and parameterizations. |
Figure 3: Close-up of Figure 1 to show relative performance of different model options in the 8-processor, 3-grid test. Plot is seconds/timestep (coarse grid timestep) vs. number of processors. |
Figure 4: Plot is efficiency vs. number of processors. Results are plotted for 2, 3, and 4 grid simulations. Also plotted are results from an 8-processor, 3-grid MM5 simulation, varying some of the model options and parameterizations. Efficiency is defined as (stime/ptime)/pnum, where stime is the time for a 1-processor simulation, ptime is the time per processor for the multi-processor simulation, and pnum is the number of processors. |
Figure 5: Plot is speed-up vs. number of processors. Results are plotted for 2, 3, and 4 grid simulations. Also plotted are results from an 8-processor, 3-grid MM5 simulation, varying some of the model options and parameterizations. Speed-up is defined as stime/ptime, where stime is the time for a 1-processor simulation and ptime is the time per processor for the multi-processor simulatiion. |
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